Through advanced semiconductor processing techniques, integrated circuit devices with submicron and sub-half-micron features sizes can now be manufactured. This trend toward deep submicron technology (i.e., involving feature sizes less than 0.35 microns) has, in turn, driven the need for multilayer interconnects. As a result, circuit performance in the deep submicron regime is increasingly a function of the delay time of electronic signals traveling between the millions of gates and transistors present on the typical integrated circuit chip. Parasitic capacitance and resistance effects resulting from these otherwise passive interconnect structures must therefore be well-controlled. Toward this end, recent trends emphasize the use of low resistance metals (e.g., copper) in conjunction with insulating materials with low dielectric constants ("low-k dielectrics") between metal lines. A low-k dielectric is a dielectric material which exhibits a dielectric constant substantially less than conventional dielectric materials such as silicon dioxide, silicon nitride, and silicon oxynitride. Silicon dioxide, for example, has a dielectric constant of about 4.0. Copper is desirable in that its conductivity is relatively high and it is less susceptible to electromigration failure than many metals (for example, aluminum).
Optical lithography techniques have, for the most part, managed to keep pace with deep submicron requirements through the use of off-axis illumination, phase shifting masks, and other methods known in the art. However, the decreasing depth of focus that accompanies this increase in resolution requires the production of highly planar surfaces during intermediary process steps. In light of the need for highly planar surfaces, traditional metal deposition and photolithographic techniques become progressively more ineffective as line widths are scaled down and multiple layers of metal are used. For example, traditional metal deposition techniques can result in poor metal step coverage along the edges of the contact openings. Furthermore, wet chemical etch processes typically used with metals are difficult to control. While dry plasma etching may be employed with many metals, other metals with highly desirable properties (e.g., copper and gold) are generally not amenable to dry etching.
Modem semiconductor processing techniques increasingly employ Chemical-Mechanical Polishing (CMP) in the fabrication of interconnect layers, particularly where the number of layers rises above three and the conductive lines themselves are characterized by a high aspect ratio (e.g., lines on the order of 0.25 .mu.m in width and on the order of 1.0 .mu.m in height). In a paradigmatic CMP process, a resinous polishing pad (e.g., a polyurethane pad) is employed in conjunction with a mechanically and chemically active slurry. When pressure is applied between the polishing pad and the wafer being polished, mechanical stresses are concentrated on the exposed edges of the adjoining cells in the cellular pad. Abrasive particles within the slurry concentrated on these edges tend to create zones of localized stress at the workpiece in the vicinity of the exposed edges of the polishing pad. This localized pressure creates mechanical strain on the chemical bonds comprising the surface being polished, rendering the chemical bonds more susceptible to chemical attack by the slurry. Thus, with the correct choice of slurry, pressure, and other process conditions, a highly planar surface may be formed on the wafer.
A fabrication method which employs CMP techniques and which addresses many of the above concerns is the so-called "damascene" process. Damascening acquired its name from an ornamental technique, generally attributed to metal-workers in ancient Damascus, which involved scribing or incising patterns into steel (most often swords) then filling the resulting grooves with gold or silver prior to final polish. Similarly, the modern semiconductor analog of this process involves, in the broadest sense, forming patterns in a dielectric layer, filling the resulting pattern with interconnect metal, then polishing away the excess metal on the wafer surface and leaving inlaid interconnect metal features.
There are two major classes of damascene processes: single-damascene and dual-damascene. These two processes are illustrated in highly simplified form in FIGS. 1A and 1B (details of the various intermediary steps are discussed in further detail below). Briefly, and with reference to FIG. 1A, a single damascene process involves making contact to a lower conductor 102 (formed, for example, on substrate 107) by patterning dielectric layer 106 and forming a conductive plug 104 in dielectric layer 106, then patterning a second dielectric layer 110 and forming the actual interconnect wiring metallization 108 in patterned dielectric layer 110. In a dual-damascene process (FIG. 1B), the interconnect wiring 108 and plug 104 are formed by patterning both the via and the trench patterns into dielectric 106, then filling them simultaneously with metal. The dual damascene process offers the advantages of process simplification and low manufacturing cost.
The use of Cu as interconnect metal in IC devices gives rise to many difficulties and challenges. For example, as is well known, placing copper in contact with silicon or silicon dioxide can lead to disastrous results. Specifically, copper tends to migrate or diffuse into the silicon dioxide, where it acts to increase leakage currents or actually short-out adjacent conductors. In addition, once Cu diffuses through the silicon dioxide and reaches the silicon devices, the device will generally malfunction in some manner. This has motivated the semiconductor industry to form diffusion barriers around any copper conductors present in the structure. The inner surfaces (i.e., the bottom and sides of the via and trench) are typically coated with a thin layer of Ti, TiN, Ta, TaN, WN or another adequate barrier metal. The top surface of a Cu conductor, however, is more difficult to deal with, as connections must be made to the top of the conductor during subsequent process steps. As a result, copper conductors are typically capped with a layer of silicon nitride after the inlaid Cu conductors are formed by CMP. Silicon nitride is desirable in that it is an effective diffusion barrier to copper and is well characterized from a processing standpoint.
As it is necessary in a dual-damascene approach to etch through the silicon nitride cap barrier layer to form a good electrical connection between the via metal and the previous level of Cu wiring, it is difficult to use silicon nitride for other purposes within the structure because these structures would necessarily be removed along with the silicon nitride cap layer material during etching. For example, it is desirable to use a "hard mask" to cover low-k dielectrics and other areas requiring protection during metal CMP. As the metal is polished away, the hard mask (typically a dielectric material) acts as a mechanical polishing stop to prevent undesirable damage to the underlying structures.
Silicon dioxide is often used as a hard mask material for the reasons set forth above with respect to the silicon nitride cap barrier layer. More particularly, it is necessary to choose a hard mask material which is different from the cap barrier layer material since the former would be removed during processing. Thus, silicon dioxide has been and continues to be the most popular choice. Unfortunately, silicon dioxide is known to exhibit a relatively high erosion rate during metal CMP. This has caused a variety of problems with respect to dual damascene copper interconnects employing low-k dielectrics. Most notably, when the oxide hard mask erodes away, the low-k material tends to delaminate or break off from the underlying structures, causing catastrophic failure.
More particularly, referring now to FIG. 2A, a typical prior art low-k dual-damascene structure (prior to metal CMP) includes copper conductors 204 formed on a substrate 202 with a dielectric (e.g., silicon dioxide or a low-k dielectric) 206. A nitride cap layer 208 is formed on copper conductors 204, which is followed by a low-k dielectric layer 210, an etch stop silicon dioxide layer 212, a second low-k dielectric layer 216, and a hard mask silicon dioxide layer 220. Using standard etching techniques, vias 228 and trenches are patterned in the low-k dielectrics, and the copper interconnect metal 230 and any seed and barrier layers are deposited to form the connection to conductor 204.
Note that, in accordance with currently known methods, cap layer 208 consists of silicon nitride and hard mask layer 220 consists of silicon dioxide. As mentioned above, the choice of silicon nitride for cap layer 208 is dictated by the need for a copper barrier, and the choice of silicon dioxide for hard mask layer 220 is based on the need to employ a material with high etch selectivity with respect to cap layer 208 (i.e., in order to etch away the silicon nitride at the bottom of via 228 without removing hard mask 220).
Referring now to FIG. 2B, which depicts the low-k structure after metal CMP, the disadvantages of this system become clear. As mentioned briefly above, silicon dioxide layer 220 exhibits poor erosion resistance to metal CMP, and thus can become extremely thin or can be removed entirely. As a result, much of the shear and other stresses arising during CMP are imparted to the underlying low-k structure; i.e., low-k layer 216. In general, low-k dielectric materials such as any of the various polymeric materials are not able to withstand CMP stresses. In addition, these low-k materials are not chemically compatible with the slurry used in Cu metal CMP. The low-k materials tend to be attacked and damaged by the slurry chemicals. Thus, it is quite common for low-k layer 216 to delaminate or separate from the underlying structure. Furthermore, even in the case where a significant thickness of oxide 220 remains after metal CMP, this oxide material may be contaminated with copper, which can affect long term reliability of the system.
This problem has emerged as a major challenge facing manufacturers seeking to develop high reliability, high performance integrated circuits. Accordingly, methods and structures are needed in order to overcome these and other limitations in the prior art.